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1.35v ddr3l sdram sodimm MT16KTF51264HZ C 4gb mt16ktf1g64hz C 8gb features ? ddr3l functionality and operations supported as defined in the component data sheet ? 204-pin, small outline dual in-line memory module (sodimm) ? fast data transfer rates: pc3-14900, pc3-12800, or pc3-10600 ? 4gb (512 meg x 64), 8gb (1 gig x 64) ? v dd = 1.35v (1.283vC1.45v) ? v dd = 1.5v (1.425C1.575v) ? backward compatible to v dd = 1.5v 0.075v ? v ddspd = 3.0C3.6v ? nominal and dynamic on-die termination (odt) for data, strobe, and mask signals ? dual rank ? fixed burst chop (bc) of 4 and burst length (bl) of 8 via the mode register set (mrs) ? on-board i 2 c serial presence-detect (spd) eeprom ? selectable bc4 or bl8 on-the-fly (otf) ? gold edge contacts ? halogen-free ? fly-by topology ? terminated control, command, and address bus figure 1: 204-pin sodimm (mo-268 r/c-f, r/c-f3) module height: 30mm (1.181in) options marking ? operating temperature C commercial (0c t a +70c) none ? package C 204-pin dimm (halogen-free) z ? frequency/cas latency C 1.07ns @ cl = 13 (ddr3-1866) -1g9 C 1.25ns @ cl = 11 (ddr3-1600) -1g6 C 1.5ns @ cl = 9 (ddr3-1333) -1g4 table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 13 cl = 11 cl = 10 cl = 9 cl = 8 cl = 7 cl = 6 cl = 5 -1g9 pc3-14900 1866 1600 1333 1333 1066 1066 800 667 13.125 13.125 47.125 -1g6 pc3-12800 C 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125 -1g4 pc3-10600 C C 1333 1333 1066 1066 800 667 13.125 13.125 49.125 -1g1 pc3-8500 C C C C 1066 1066 800 667 13.125 13.125 50.625 -1g0 pc3-8500 C C C C 1066 C 800 667 15 15 52.5 -80b pc3-6400 C C C C C C 800 667 15 15 52.5 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm features pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing parameter 4gb 8gb refresh count 8k 8k row address 32k a[14:0] 64k a[15:0] device bank address 8 ba[2:0] 8 ba[2:0] device configuration 2gb (256 meg x 8) 4gb (512 meg x8) column address 1k a[9:0] 1k a[9:0] module rank address 2 s#[1:0] 2 s#[1:0] table 3: part numbers and timing parameters C 4gb modules base device: mt41k256m8, 1 2gb 1.35v ddr3l sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) MT16KTF51264HZ-1g6__ 4gb 512 meg x 64 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 MT16KTF51264HZ-1g4__ 4gb 512 meg x 64 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 table 4: part numbers and timing parameters C 8gb modules base device: mt41k512m8, 1 4gb 1.35v ddr3l sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt16ktf1g64hz-1g9__ 8gb 1 gig x 64 14.9 gb/s 1.07ns/1866 mt/s 13-13-13 mt16ktf1g64hz-1g6__ 8gb 1 gig x 64 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 mt16ktf1g64hz-1g4__ 8gb 1 gig x 64 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 notes: 1. the data sheet for the base device can be found on microns web site. 2. all part numbers end with a two-place code (not shown) that designates component and pcb revisions. con- sult factory for current revision codes. example: mt16ktf1g64hz-1g9 n1. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm features pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
pin assignments table 5: pin assignments 204-pin ddr3 sodimm front 204-pin ddr3 sodimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 v refdq 53 dq19 105 v dd 157 dq42 2 v ss 54 v ss 106 v dd 158 dq46 3 v ss 55 v ss 107 a10 159 dq43 4 dq4 56 dq28 108 ba1 160 dq47 5 dq0 57 dq24 109 ba0 161 v ss 6 dq5 58 dq29 110 ras# 162 v ss 7 dq1 59 dq25 111 v dd 163 dq48 8 v ss 60 v ss 112 v dd 164 dq52 9 v ss 61 v ss 113 we# 165 dq49 10 dqs0# 62 dqs3# 114 s0# 166 dq53 11 dm0 63 dm3 115 cas# 167 v ss 12 dqs0 64 dqs3 116 odt0 168 v ss 13 v ss 65 v ss 117 v dd 169 dqs6# 14 v ss 66 v ss 118 v dd 170 dm6 15 dq2 67 dq26 119 a13 171 dqs6 16 dq6 68 dq30 120 odt1 172 v ss 17 dq3 69 dq27 121 s1# 173 v ss 18 dq7 70 dq31 122 nc 174 dq54 19 v ss 71 v ss 123 v dd 175 dq50 20 v ss 72 v ss 124 v dd 176 dq55 21 dq8 73 cke0 125 nc 177 dq51 22 dq12 74 cke1 126 v refca 178 v ss 23 dq9 75 v dd 127 v ss 179 v ss 24 dq13 76 v dd 128 v ss 180 dq60 25 v ss 77 nc 129 dq32 181 dq56 26 v ss 78 nc/a15 1 130 dq36 182 dq61 27 dqs1# 79 ba2 131 dq33 183 dq57 28 dm1 80 a14 132 dq37 184 v ss 29 dqs1 81 v dd 133 v ss 185 v ss 30 reset# 82 v dd 134 v ss 186 dqs7# 31 v ss 83 a12 135 dqs4# 187 dm7 32 v ss 84 a11 136 dm4 188 dqs7 33 dq10 85 a9 137 dqs4 189 v ss 34 dq14 86 a7 138 v ss 190 v ss 35 dq11 87 v dd 139 v ss 191 dq58 36 dq15 88 v dd 140 dq38 192 dq62 37 v ss 89 a8 141 dq34 193 dq59 38 v ss 90 a6 142 dq39 194 dq63 39 dq16 91 a5 143 dq35 195 v ss 40 dq20 92 a4 144 v ss 196 v ss 41 dq17 93 v dd 145 v ss 197 sa0 42 dq21 94 v dd 146 dq44 198 nf 43 v ss 95 a3 147 dq40 199 v ddspd 44 v ss 96 a2 148 dq45 200 sda 45 dqs2# 97 a1 149 dq41 201 sa1 46 dm2 98 a0 150 v ss 202 scl 47 dqs2 99 v dd 151 v ss 203 v tt 48 v ss 100 v dd 152 dqs5# 204 v tt 49 v ss 101 ck0 153 dm5 C C 50 dq22 102 ck1 154 dqs5 C C 51 dq18 103 ck0# 155 v ss C C 52 dq23 104 ck1# 156 v ss C C note: 1. pin 78 is nc 4gb, a15 for 8gb. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm pin assignments pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
pin descriptions the pin description table below is a comprehensive list of all possible pins for all ddr3 modules. all pins listed may not be supported on this module. see pin assignments for information specific to this module. table 6: pin descriptions symbol type description ax input address inputs: provide the row address for active commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by bax) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. see the pin assignments table for density-specific ad- dressing information. bax input bank address inputs: define the device bank to which an active, read, write, or precharge command is being applied. ba define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ckx, ckx# input clock: differential clock inputs. all control, command, and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. ckex input clock enable: enables (registered high) and disables (registered low) internal circui- try and clocks on the dram. dmx input data mask (x8 devices only): dm is an input mask signal for write data. input data is masked when dm is sampled high, along with that input data, during a write ac- cess. although dm pins are input-only, dm loading is designed to match that of the dq and dqs pins. odtx input on-die termination: enables (registered high) and disables (registered low) termi- nation resistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to the following pins: dq, dqs, dqs#, dm, and cb. the odt input will be ignored if disabled via the load mode command. par_in input parity input: parity bit for ax, ras#, cas#, and we#. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input (lvcmos) reset: reset# is an active low asychronous input that is connected to each dram and the registering clock driver. after reset# goes high, the dram must be reinitial- ized as though a normal power-up was executed. sx# input chip select: enables (registered low) and disables (registered high) the command decoder. sax input serial address inputs: used to configure the temperature sensor/spd eeprom ad- dress range on the i 2 c bus. scl input serial clock for temperature sensor/spd eeprom: used to synchronize communi- cation to and from the temperature sensor/spd eeprom on the i 2 c bus. cbx i/o check bits: used for system error detection and correction. dqx i/o data input/output: bidirectional data bus. dqsx, dqsx# i/o data strobe: differential data strobes. output with read data; edge-aligned with read data; input with write data; center-aligned with write data. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm pin descriptions pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 6: pin descriptions (continued) symbol type description sda i/o serial data: used to transfer addresses and data into and out of the temperature sen- sor/spd eeprom on the i 2 c bus. tdqsx, tdqsx# output redundant data strobe (x8 devices only): tdqs is enabled/disabled via the load mode command to the extended mode register (emr). when tdqs is enabled, dm is disabled and tdqs and tdqs# provide termination resistance; otherwise, tdqs# are no function. err_out# output (open drain) parity error output: parity error found on the command and address bus. event# output (open drain) temperature event: the event# pin is asserted by the temperature sensor when crit- ical temperature thresholds have been exceeded. v dd supply power supply: 1.35v (1.283C1.45v) backward-compatible to 1.5v (1.425C1.575v). the component v dd and v ddq are connected to the module v dd . v ddspd supply temperature sensor/spd eeprom power supply: 3.0C3.6v. v refca supply reference voltage: control, command, and address v dd /2. v refdq supply reference voltage: dq, dm v dd /2. v ss supply ground. v tt supply termination voltage: used for control, command, and address v dd /2. nc C no connect: these pins are not connected on the module. nf C no function: these pins are connected within the module, but provide no functional- ity. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm pin descriptions pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
dq map table 7: component-to-module dq map, pcb 0900 r/c-f (front) component reference number component dq module dq module pin number component reference number component dq module dq module pin number u1 0 2 15 u2 0 18 51 1 5 6 1 21 42 2 3 17 2 19 53 3 0 5 3 16 39 4 6 16 4 22 50 5 4 4 5 20 40 6 7 18 6 23 52 7 1 7 7 17 41 u5 0 42 157 u6 0 58 191 1 45 148 1 61 182 2 43 159 2 59 193 3 40 147 3 56 181 4 46 158 4 62 192 5 44 146 5 60 180 6 47 160 6 63 194 7 41 149 7 57 183 u7 0 13 24 u8 0 26 67 1 10 33 1 29 58 2 8 21 2 27 69 3 11 35 3 24 57 4 9 23 4 30 68 5 15 36 5 28 56 6 12 22 6 31 70 7 14 34 7 25 59 u9 0 34 141 u10 0 53 166 1 37 132 1 50 175 2 35 143 2 48 163 3 32 129 3 51 177 4 38 140 4 49 165 5 36 130 5 55 176 6 39 142 6 52 164 7 33 131 7 54 174 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm dq map pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 8: component-to-module dq map, pcb 0900 r/c-f (back) component reference number component dq module dq module pin number component reference number component dq module dq module pin number u11 0 61 182 u12 0 45 148 1 58 191 1 42 157 2 56 181 2 40 147 3 59 193 3 43 159 4 57 183 4 41 149 5 63 194 5 47 160 6 60 180 6 44 146 7 62 192 7 46 158 u15 0 21 42 u16 0 5 6 1 18 51 1 2 15 2 16 39 2 0 5 3 19 53 3 3 17 4 17 41 4 1 7 5 23 52 5 7 18 6 20 40 6 4 4 7 22 50 7 6 16 u17 0 50 175 u18 0 37 132 1 53 166 1 34 141 2 51 177 2 32 129 3 48 163 3 35 143 4 54 174 4 33 131 5 52 164 5 39 142 6 55 176 6 36 130 7 49 165 7 38 140 u19 0 29 58 u20 0 10 33 1 26 67 1 13 24 2 24 57 2 11 35 3 27 69 3 8 21 4 25 59 4 14 34 5 31 70 5 12 22 6 28 56 6 15 36 7 30 68 7 9 23 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm dq map pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 9: component-to-module dq map, pcb 1569 r/c-f3 (front) component reference number component dq module dq module pin number component reference number component dq module dq module pin number u2 0 2 13 u3 0 18 49 1 5 6 1 21 42 2 3 15 2 19 51 3 0 5 3 16 37 4 6 16 4 22 48 5 4 4 5 20 40 6 7 18 6 23 50 7 1 7 7 17 39 u4 0 42 159 u5 0 58 191 1 45 150 1 61 182 2 43 161 2 59 193 3 40 151 3 56 183 4 46 160 4 62 192 5 44 148 5 60 180 6 47 162 6 63 194 7 41 153 7 57 185 u6 0 13 24 u7 0 26 63 1 10 31 1 29 56 2 8 19 2 27 65 3 11 33 3 24 55 4 9 21 4 30 66 5 15 36 5 28 54 6 12 22 6 31 68 7 14 34 7 25 57 u8 0 34 145 u9 0 53 168 1 37 136 1 50 177 2 35 147 2 48 165 3 32 133 3 51 179 4 38 142 4 49 167 5 36 134 5 55 176 6 39 144 6 52 166 7 33 135 7 54 174 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm dq map pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 10: component-to-module dq map, pcb 1569 r/c-f (back) component reference number component dq module dq module pin number component reference number component dq module dq module pin number u11 0 61 182 u12 0 45 150 1 58 191 1 42 159 2 56 183 2 40 151 3 59 193 3 43 161 4 57 185 4 41 153 5 63 194 5 47 162 6 60 180 6 44 148 7 62 192 7 46 160 u13 0 21 42 u14 0 5 6 1 18 49 1 2 13 2 16 37 2 0 5 3 19 51 3 3 15 4 17 39 4 1 7 5 23 50 5 7 18 6 20 40 6 4 4 7 22 48 7 6 16 u15 0 50 177 u16 0 37 136 1 53 168 1 34 145 2 51 179 2 32 133 3 48 165 3 35 147 4 54 174 4 33 135 5 52 166 5 39 144 6 55 176 6 36 134 7 49 167 7 38 142 u17 0 29 56 u18 0 10 31 1 26 63 1 13 24 2 24 55 2 11 33 3 27 65 3 8 19 4 25 57 4 14 34 5 31 68 5 12 22 6 28 54 6 15 36 7 30 66 7 9 21 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm dq map pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
functional block diagram figure 2: functional block diagram (pcb 0900, r/c-f) dq dq dq dq dq dq dq dq zq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u1 dm cs# dq dqs# dq dq dq dq dq dq dq dq u16 dq dq dq dq dq dq dq dq zq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 u9 dq dq dq dq dq dq dq dq u18 dm cs# dq dqs# dm cs# dq dqs# dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 u7 dm cs# dq dqs# dq dq dq dq dq dq dq dq u20 dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 dm cs# dq dqs# dq dq dq dq dq dq dq dq u15 dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u19 dm cs# dq dqs# dq dq dq dq dq dq dq dq u8 dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u12 dq dq dq dq dq dq dq dq u5 dm cs# dq dqs# dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u17 dq dq dq dq dq dq dq dq u10 dm cs# dq dqs# dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u11 dq dq dq dq dq dq dq dq u6 dm cs# dq dqs# dm cs# dq dqs# dqs0# dqs0 dm0 s0# s1# dqs1# dqs1 dm1 dqs2# dqs2 dm2 dqs3# dqs3 dm3 dqs4# dqs4 dm4 dqs5# dqs5 dm5 dqs6# dqs6 dm6 dqs7# dqs7 dm7 ba[2:0] a[15/14:0] ras# cas# we# cke0 cke1 odt0 odt1 reset# ba[2:0]: ddr3 sdram a[15/14:0]: ddr3 sdram ras#: ddr3 sdram cas#: ddr3 sdram we#: ddr3 sdram cke0: rank 0 cke1: rank 1 odt0: rank 0 odt1: rank 1 reset#: ddr3 sdram rank 0 ck0 ck0# ck1 ck1# v refca v ss ddr3 sdram ddr3 sdram v dd ddr3 sdram v ddspd spd eeprom v tt ddr3 sdram ddr3 sdram v refdq command, address and clock line terminations ck[1:0] ck#[1:0] rank 0 = u1, u2, u7, u9, u11, u12, u17, u19 rank 1 = u5, u6, u8, u10, u15, u16, u18, u20 rank 1 v ss zq v ss zq v ss zq v ss zq v ss zq v ss zq v ss zq v ss zq v ss v ss v ss v ss v ss v ss v ss v ss ddr3 sdram v tt ddr3 sdram v dd a0 spd eeprom a1 a2 sa0 sa1 sda wp u14 v ss v ss scl cke[1:0], a[15/14:0], ras#, cas#, we#, s#[1:0], odt[1:0], ba[2:0] note: 1. the zq ball on each ddr3 component is connected to an external 240 1% resistor that is tied to ground. it is used for the calibration of the components odt and output driver. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm functional block diagram pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 3: functional block diagram (pcb 1569, r/c-f3) dq dq dq dq dq dq dq dq zq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u2 dm cs# dq dqs# dq dq dq dq dq dq dq dq u14 dq dq dq dq dq dq dq dq zq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 u8 dq dq dq dq dq dq dq dq u16 dm cs# dq dqs# dm cs# dq dqs# dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 u6 dm cs# dq dqs# dq dq dq dq dq dq dq dq u18 dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u3 dm cs# dq dqs# dq dq dq dq dq dq dq dq u13 dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u17 dm cs# dq dqs# dq dq dq dq dq dq dq dq u7 dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u12 dq dq dq dq dq dq dq dq u4 dm cs# dq dqs# dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u15 dq dq dq dq dq dq dq dq u9 dm cs# dq dqs# dm cs# dq dqs# dq dq dq dq dq dq dq dq zq dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u11 dq dq dq dq dq dq dq dq u5 dm cs# dq dqs# dm cs# dq dqs# dqs0# dqs0 dm0 s0# s1# dqs1# dqs1 dm1 dqs2# dqs2 dm2 dqs3# dqs3 dm3 dqs4# dqs4 dm4 dqs5# dqs5 dm5 dqs6# dqs6 dm6 dqs7# dqs7 dm7 ba[2:0] a[14:0] ras# cas# we# cke0 cke1 odt0 odt1 reset# ba[2:0]: ddr3 sdram a[14:0]: ddr3 sdram ras#: ddr3 sdram cas#: ddr3 sdram we#: ddr3 sdram cke0: rank 0 cke1: rank 1 odt0: rank 0 odt1: rank 1 reset#: ddr3 sdram rank 0 ck0 ck0# ck1 ck1# v refca v ss ddr3 sdram ddr3 sdram v dd ddr3 sdram v ddspd spd eeprom v tt ddr3 sdram ddr3 sdram v refdq command, address and clock line terminations cke[1:0], a[14:0], ras#, cas#, we#, odt[1:0], ba[2:0] ck[1:0] ck#[1:0] rank 0 = u2, u3, u6, u7, u8, u11, u12, u15 rank 1 = u4, u5, u7, u19, u13, u14, u16, u18 rank 1 v ss zq v ss zq v ss zq v ss zq v ss zq v ss zq v ss zq v ss zq v ss v ss v ss v ss v ss v ss v ss v ss ddr3 sdram v tt ddr3 sdram v dd a0 spd eeprom a1 a2 sa0 sa1 sda wp u10 v ss v ss scl note: 1. the zq ball on each ddr3 component is connected to an external 240 1% resistor that is tied to ground. it is used for the calibration of the components odt and output driver. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm functional block diagram pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
general description ddr3 sdram modules are high-speed, cmos dynamic random access memory mod- ules that use internally configured 8-bank ddr3 sdram devices. ddr3 sdram mod- ules use ddr architecture to achieve high-speed operation. ddr3 architecture is essen- tially an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr3 sdram mod- ule effectively consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the inter- nal dram core and eight corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o pins. ddr3 modules use two sets of differential signals: dqs, dqs# to capture data and ck and ck# to capture commands, addresses, and control signals. differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. fly-by topology ddr3 modules use faster clock speeds than earlier ddr technologies, making signal quality more important than ever. for improved signal quality, the clock, control, com- mand, and address buses have been routed in a fly-by topology, where each clock, con- trol, command, and address pin on each dram is connected to a single trace and ter- minated (rather than a tree structure, where the termination is off the module near the connector). inherent to fly-by topology, the timing skew between the clock and dqs sig- nals can be easily accounted for by using the write-leveling feature of ddr3. serial presence-detect eeprom operation ddr3 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are programmed by micron to comply with jedec standard jc-45, "appendix x: serial presence detect (spd) for ddr3 sdram modules." these bytes identify module-specific timing parameters, configuration infor- mation, and physical attributes. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimms scl (clock) sda (data), and sa (address) pins. write protect (wp) is connected to v ss , per- manently disabling hardware write protection. for further information refer to micron technical note tn-04-42, "memory module serial presence-detect." 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm general description pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed may cause permanent damage to the module. this is a stress rating only, and functional operation of the module at these or any other condi- tions outside those indicated in each device's data sheet is not implied. exposure to ab- solute maximum rating conditions for extended periods may adversely affect reliability. table 11: absolute maximum ratings symbol parameter min max units v dd v dd supply voltage relative to v ss C0.4 1.975 v v in , v out voltage on any pin relative to v ss C0.4 1.975 v table 12: operating conditions symbol parameter min nom max units notes v dd v dd supply voltage 1.283 1.35 1.45 v 1.425 1.5 1.575 v 1 i vtt termination reference current from v tt C600 C 600 ma v tt termination reference voltage (dc) C com- mand/address bus 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v 2 i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) address inputs, ras#, cas#, we#, ba C32 0 32 a s#, cke, odt, ck, ck# C16 0 16 dm C4 0 4 i oz output leakage current; 0v v out v dd ; dq and odt are disabled; odt is high dq, dqs, dqs# C10 0 10 a i vref v ref supply leakage current; v refdq = v dd /2 or v refca = v dd /2 (all other pins not under test = 0v) C16 0 16 a t a module ambient operating temperature commercial 0 C 70 c 3, 4 t c ddr3 sdram component case operating temperature commercial 0 C 95 c 3, 4, 5 notes: 1. module is backward-compatible with 1.5v operation. refer to device specification for details and operation guidance. 2. v tt termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins. 3. t a and t c are simultaneous requirements. 4. for further information, refer to technical note tn-00-08: thermal applications, available on microns web site. 5. the refresh rate is required to double when 85c < t c 95c. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm electrical specifications pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
dram operating conditions recommended ac operating conditions are given in the ddr3 component data sheets. component specifications are available at micron.com. module speed grades correlate with component speed grades, as shown below. table 13: module and component speed grades ddr3 components may exceed the listed module speed grades; module may not be available in all listed speed grades module speed grade component speed grade -2g1 -093 -1g9 -107 -1g6 -125 -1g4 -15e -1g1 -187e -1g0 -187 -80c -25e -80b -25 design considerations simulations micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good signal integrity starts at the system level. micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram, not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to en- sure the required supply voltage is maintained. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm dram operating conditions pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
i dd specifications table 14: ddr3 i dd specifications and conditions C 4gb (die revision k) values are for the mt41k256m8 ddr3l sdram only and are computed from values specified in the 1.35v 2gb (256 meg x 8) component data sheet parameter symbol 1600 1333 units operating current 0: one bank activate-to-precharge i dd0 1 408 400 ma operating current 1: one bank activate-to-read-to-precharge i dd1 1 512 496 ma precharge power-down current: slow exit i dd2p0 2 192 192 ma precharge power-down current: fast exit i dd2p1 2 224 224 ma precharge quiet standby current i dd2q 2 320 320 ma precharge standby current i dd2n 2 336 336 ma precharge standby odt current i dd2nt 1 344 328 ma active power-down current i dd3p 2 336 336 ma active standby current i dd3n 2 512 480 ma burst read operating current i dd4r 1 848 752 ma burst write operating current i dd4w 1 872 776 ma refresh current i dd5b 1 1536 1528 ma self refresh temperature current: max t c = 85c i dd6 2 192 192 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 2 240 240 ma all banks interleaved read current i dd7 1 1344 1296 ma reset current i dd8 2 224 224 ma notes: 1. one module rank in the active i dd ; the other rank in i dd2p0 (slow exit). 2. all ranks in this i dd condition. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm i dd specifications pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 15: ddr3 i dd specifications and conditions C 8gb (die revisions e) values are for the mt41k512m8 ddr3l sdram only and are computed from values specified in the 1.35v 4gb (512 meg x 8) component data sheet parameter symbol 1866 1600 1333 units operating current 0: one bank activate-to-precharge i dd0 1 640 584 520 ma operating current 1: one bank activate-to-read-to-precharge i dd1 1 704 672 640 ma precharge power-down current: slow exit i dd2p0 2 288 288 288 ma precharge power-down current: fast exit i dd2p1 2 592 512 448 ma precharge quiet standby current i dd2q 2 560 512 448 ma precharge standby current i dd2n 2 560 512 464 ma precharge standby odt current i dd2nt 1 480 456 424 ma active power-down current i dd3p 2 656 608 560 ma active standby current i dd3n 2 656 608 560 ma burst read operating current i dd4r 1 1536 1400 1264 ma burst write operating current i dd4w 1 1272 1144 1024 ma refresh current i dd5b 1 2080 2024 1968 ma self refresh temperature current: max t c = 85c i dd6 2 320 320 320 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 2 400 400 400 ma all banks interleaved read current i dd7 1 2152 1904 1664 ma reset current i dd8 2 320 320 320 ma notes: 1. one module rank in the active i dd ; the other rank in i dd2p0 (slow exit). 2. all ranks in this i dd condition. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm i dd specifications pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 16: ddr3 i dd specifications and conditions C 8gb (die revision n) values are for the mt41k512m8 ddr3l sdram only and are computed from values specified in the 1.35v 4gb (512 meg x 8) component data sheet parameter symbol 1866 1600 units operating current 0: one bank activate-to-precharge i dd0 1 456 440 ma operating current 1: one bank activate-to-read-to-precharge i dd1 1 576 552 ma precharge power-down current: slow exit i dd2p0 2 128 128 ma precharge power-down current: fast exit i dd2p1 2 256 224 ma precharge quiet standby current i dd2q 2 416 384 ma precharge standby current i dd2n 2 416 384 ma precharge standby odt current i dd2nt 1 304 288 ma active power-down current i dd3p 2 448 416 ma active standby current i dd3n 2 512 480 ma burst read operating current i dd4r 1 904 824 ma burst write operating current i dd4w 1 904 824 ma refresh current i dd5b 1 1504 1464 ma self refresh temperature current: max t c = 85c i dd6 2 192 192 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 2 256 256 ma all banks interleaved read current i dd7 1 1184 1104 ma reset current i dd8 2 160 160 ma notes: 1. one module rank in the active i dd ; the other rank in i dd2p0 (slow exit). 2. all ranks in this i dd condition. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm i dd specifications pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 17: ddr3 i dd specifications and conditions C 8gb (die revision p) values are for the mt41k512m8 ddr3l sdram only and are computed from values specified in the 1.35v 4gb (512 meg x 8) component data sheet parameter symbol 1866 1600 units operating current 0: one bank activate-to-precharge i dd0 1 320 304 ma operating current 1: one bank activate-to-read-to-precharge i dd1 1 440 424 ma precharge power-down current: slow exit i dd2p0 2 176 160 ma precharge power-down current: fast exit i dd2p1 2 176 176 ma precharge quiet standby current i dd2q 2 240 240 ma precharge standby current i dd2n 2 272 256 ma precharge standby odt current i dd2nt 1 264 240 ma active power-down current i dd3p 2 240 240 ma active standby current i dd3n 2 336 320 ma burst read operating current i dd4r 1 904 800 ma burst write operating current i dd4w 1 992 888 ma refresh current i dd5b 1 1304 1296 ma self refresh temperature current: max t c = 85c i dd6 2 240 240 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 2 368 368 ma all banks interleaved read current i dd7 1 1256 1120 ma reset current i dd8 2 208 208 ma notes: 1. one module rank in the active i dd ; the other rank in i dd2p0 (slow exit). 2. all ranks in this i dd condition. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm i dd specifications pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
serial presence-detect eeprom for the latest spd data, refer to micron's spd page: micron.com/spd. table 18: serial presence-detect eeprom dc operating conditions all voltages referenced to v ddspd parameter/condition symbol min max units supply voltage v ddspd 3.0 3.6 v input low voltage: logic 0; all inputs v il C0.45 v ddspd x 0.3 v input high voltage: logic 1; all inputs v ih v ddspd x 0.7 v ddspd + 1.0 v output low voltage: i out = 3ma v ol C 0.4 v input leakage current: v in = gnd to v dd i li 0.1 2.0 a output leakage current: v out = gnd to v dd i lo 0.05 2.0 a table 19: serial presence-detect eeprom ac operating conditions parameter/condition symbol min max units notes clock frequency t scl 10 400 khz clock pulse width high time t high 0.6 C s clock pulse width low time t low 1.3 C s sda rise time t r C 300 s 1 sda fall time t f 20 300 ns 1 data-in setup time t su:dat 100 C ns data-in hold time t hd:di 0 C s data-out hold time t hd:dat 200 900 ns data out access time from scl low t aa:dat 0.2 0.9 s 2 start condition setup time t su:sta 0.6 C s 3 start condition hold time t hd:sta 0.6 C s stop condition setup time t su:sto 0.6 C s time the bus must be free before a new transition can start t buf 1.3 C s write time t w C 10 ms notes: 1. guaranteed by design and characterization, not necessarily tested. 2. to avoid spurious start and stop conditions, a minimum delay is placed between the fall- ing edge of scl and the falling or rising edge of sda. 3. for a restart condition, or following a write cycle. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm serial presence-detect eeprom pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
module dimensions figure 4: 204-pin ddr3 sodimm (pcb 0900, r/c-f) 3.8 (0.150) max pin 1 67.75 (2.667) 67.45 (2.656) 20.0 (0.787) typ 1.8 (0.071) (2x) 0.6 (0.024) typ 0.45 (0.018) typ 2.0 (0.079) r (2x) pin 203 pin 204 pin 2 front view 2.0 (0.079) typ 6.0 (0.236) typ 63.6 (2.504) typ 2.55 (0.10) typ 1.0 (0.039) typ 30.15 (1.187) 29.85 (1.175) back view 1.10 (0.043) 0.90 (0.035) 39.0 (1.535) typ 21.0 (0.827) typ 3.0 (0.12) typ 4.0 (0.157) typ 24.8 (0.976) typ u1 u2 u7 u8 u5 u9 u6 u10 u11 u17 u12 u18 u15 u14 u19 u16 u20 45 4x notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm module dimensions pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 5: 204-pin ddr3 sodimm (pcb 1569, r/c-f3) 3.8 (0.150) max pin 1 67.75 (2.667) 67.45 (2.656) 20.0 (0.787) typ 1.8 (0.071) (2x) 0.6 (0.024) typ 0.45 (0.018) typ 2.0 (0.079) r (2x) pin 203 pin 204 pin 2 front view 2.0 (0.079) typ 6.0 (0.236) typ 63.6 (2.504) typ 2.55 (0.10) typ 1.0 (0.039) typ 30.15 (1.187) 29.85 (1.175) back view 1.10 (0.043) 0.90 (0.035) 39.0 (1.535) typ 21.0 (0.827) typ 3.0 (0.12) typ 4.0 (0.157) typ 24.8 (0.976) typ u2 u3 u6 u7 u4 u8 u5 u9 u11 u15 u12 u16 u13 u10 u17 u14 u18 45 4x notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-4000 www.micron.com/products/support sales inquiries: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 4gb, 8gb (x64, dr) 204-pin 1.35v ddr3l sodimm module dimensions pdf: 09005aef846206a0 ktf16c512_1gx64hz.pdf - rev. k 7/15 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.

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